Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test

Author

Yen, Cheng-Cheng ; Ker, Ming-Dou ; Chen, Tung-Yang

Author_Institution

Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao Tung Univ., Hsinchu

Volume

9

Issue

2

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

255

Lastpage

264

Abstract

The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (ICs) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-mum CMOS process was used in EFT tests. For physical mechanism characterization, the specific ldquoswept-backrdquo current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.

Keywords

CMOS digital integrated circuits; flip-flops; integrated circuit noise; integrated circuit testing; minority carriers; thyristors; CMOS integrated circuit; EFT test; PNPN structure; board-level noise filter network; electrical fast-transient test; silicon-controlled-rectifier; size 0.18 mum; transient-induced latchup; Board-level noise filter; electrical fast transient (EFT); latchup; silicon-controlled rectifier (SCR); transient-induced latchup (TLU);

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2009.2015938

Filename

4799110