Special hardware for computing the probability of undetected error for certain binary CRC codes and test results

Author

Chun, Dexter ; Wolf, Jack Keil

Author_Institution

Qualcomm Inc., San Diego, CA, USA

Volume

42

Issue

10

fYear

1994

fDate

10/1/1994 12:00:00 AM

Firstpage

2769

Lastpage

2772

Abstract

A hardware device for efficiently evaluating the probability of undetected error for a class of CRC error detection codes with a large number of parity check digits is described. The generator polynomial for the codes in this class are of the form g(x)=(1+x)p(x) where p(x) is a primitive irreducible polynomial. The degree of g(x), R, is the number of parity check digits. Using this hardware, a search was conducted for codes in this class (for 8⩽R⩽39) which are “proper” for shortened block lengths. A table of codes satisfying this condition is included

Keywords

binary sequences; block codes; coding errors; cyclic codes; digital circuits; error detection codes; error statistics; polynomials; probability; redundancy; search problems; binary CRC codes; cyclic redundancy check codes; error detection codes; generator polynomial; hardware device; parity check digits; primitive irreducible polynomial; shortened block lengths; test results; undetected error probability; Axles; Code standards; Communication channels; Communication standards; Cyclic redundancy check; Error probability; Hamming weight; Hardware; Linear code; Testing;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.328943

Filename

328943