Title :
Effect of N-well for single event upset in 65 nm CMOS triple-well technology in 6T SRAM CELLS
Author :
Jian Wang ; Lei Li
Author_Institution :
Res. Inst. of Electron. Sci. & Technol., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
In this paper, the effect of N-well for single event upset in 65nm CMOS triple well technology SRAM CELLS is studied. The study shows that charge sharing collection increases because of the existing of N-well in triple-well technology. While it restrains the single event upset and reduces the soft error rate (SER) compared with the SRAM whose NMOS are dual-well technology devices. The result of this work can provide a way to protect integration circuits from single event effect (SEE) and soft errors.
Keywords :
CMOS digital integrated circuits; SRAM chips; radiation hardening (electronics); 6T SRAM cells; CMOS triple well technology; N-well; SEE; SER reduction; charge sharing collection; integration circuit protection; single event effect; single event upset; size 65 nm; soft error rate reduction; CMOS integrated circuits; Electric potential; Integrated circuit modeling; MOS devices; SRAM cells; Single event upsets; SRAM; single event upset (SET); triple-well technology;
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2014 15th International Conference on
Conference_Location :
Chengdu
DOI :
10.1109/ICEPT.2014.6922840
