Title :
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves
Author :
Sato, Takashi ; Cao, Yu ; Agarwal, Kanak ; Sylvester, Dennis ; Hu, Chenming
Author_Institution :
Hitachi Ltd., Tokyo, Japan
fDate :
5/1/2003 12:00:00 AM
Abstract :
A novel concept of bidirectional transformation between on-chip coupling noise waveform and delay-change curve (DCC) using closed-form equations is described in this paper. These equations are targeted for use in: 1) the efficient generation of DCCs and 2) accurate experimental determination of subnanosecond coupling noise. In particular, we explore the concept of using analytical models to efficiently generate DCCs that can then be used to characterize the impact of noise on any victim/aggressor configuration. The concept is model independent, although we investigate several common noise modeling choices and perform a sensitivity analysis to optimize the generation of DCCs. By extending existing noise models, arbitrary configurations can be considered including multiple aggressors in the timing-analysis framework. Simulation using the analytical approach closely matches time-consuming SPICE simulations, making noise-aware timing analysis using DCCs both efficient and accurate. A test chip using a 0.25-μm CMOS process was designed and its measurement results also show good agreement with SPICE simulations.
Keywords :
CMOS digital integrated circuits; crosstalk; delay estimation; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; sensitivity analysis; timing; 0.25 micron; CMOS process; analytical models; bidirectional closed-form transformation; closed-form equations; crosstalk noise; interconnect delay-change curves; noise models; noise-aware timing analysis; on-chip coupling noise waveforms; sensitivity analysis; subnanosecond coupling noise; timing-analysis framework; victim/aggressor configuration; Analytical models; Character generation; Equations; Noise generators; Propagation delay; SPICE; Semiconductor device modeling; Sensitivity analysis; Testing; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.810750