Title :
Multistage shuffle networks with shortest path and deflection routing for high-performance ATM switching: the closed-loop shuffleout
Author :
Decina, M. ; Giacomazzi, Paolo ; Pattavina, Achille
Author_Institution :
Dept. of Electron. & Inf., Politecnico di Milano, Italy
fDate :
11/1/1994 12:00:00 AM
Abstract :
A new class of switching architectures for broadband packet networks, called shuffleout, is described and analyzed. Shuffleout is basically an output-queued architecture with a multistage interconnection network built out of unbuffered b×2b switching elements. Its structure is such that the number of cells that can be concurrently switched from the inlets to each output queue equals the number of stages in the interconnection network. The switching element operates the cell self-routing adopting a shortest path algorithm which, in case of conflict for interstage links, is coupled with deflection routing. The basic version of this architecture is called open-loop shuffleout. This paper describes the closed-loop shuffleout architecture with 2×4 switching elements in which cells that have crossed the whole interconnection network re-enter the network as long as they are not successfully routed to the addressed switch outlet. This result is accomplished by adding to the basic open-loop structure recirculation paths so that each packet can cross several times the interconnection network. Two different solutions are proposed to implement such functionality, the buffered closed-loop shuffleout and the expanded closed-loop shuffleout architecture. Both these solutions aim at reducing the number of stages in the network, compared to the open-loop structure, so as to reduce the complexity of the switch internal wiring and to simplify the output queue interface
Keywords :
asynchronous transfer mode; broadband networks; electronic switching systems; packet switching; queueing theory; switching networks; telecommunication network routing; ATM switching; broadband packet networks; buffered closed-loop shuffleout; cell self-routing; closed-loop shuffleout; deflection routing; expanded closed-loop shuffleout; multistage interconnection network; multistage shuffle networks; output queue interface; output-queued architecture; shortest path algorithm; shortest path routing; switching architectures; unbuffered switching elements; Asynchronous transfer mode; Communication switching; Communications Society; Multiprocessor interconnection networks; Packet switching; Routing; Senior members; Switches; Taxonomy; Wiring;
Journal_Title :
Communications, IEEE Transactions on