DocumentCode :
1188459
Title :
Accurate crosstalk noise modeling for early signal integrity analysis
Author :
Ding, Li ; Blaauw, David ; Mazumder, Pinaki
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
Volume :
22
Issue :
5
fYear :
2003
fDate :
5/1/2003 12:00:00 AM
Firstpage :
627
Lastpage :
634
Abstract :
In this paper, we propose an accurate and fast method to estimate the crosstalk noise in the presence of multiple aggressor nets for use in physical design automation tools. Since noise estimation is often part of the inner loop of optimization algorithms, very efficient closed-form solutions are needed. Previous approaches model aggressor nets one at a time, assuming that the coupling capacitance to all quiet aggressor nets are grounded. They also model the load from interconnect branches as a lumped capacitor, the value of which is the sum of interconnect and load capacitances of the branch. Finally, previous works typically use simple lumped 2-4-node circuit templates and employ a so-called dominant pole approximation to solve the template circuit. While these approximations allow for very fast analysis, they may result in significant underestimation of the noise. In this paper, we propose a new and more comprehensive fast noise estimation method. We propose a novel reduction technique for modeling quiet aggressor nets based on the concept of coupling point admittance. We also propose a reduction method to replace tree branches with effective capacitors which models the effect of resistive shielding. Furthermore, we model the simplified single aggressor net crosstalk noise problem using a 6-node template circuit and propose a new double pole approach to solve the template circuit. We have tested the proposed method on noise-prone interconnects from an industrial high-performance processor. Our results show a worst case error of 7.8% and an average error of 2.7%, while allowing for very fast analysis.
Keywords :
CMOS digital integrated circuits; VLSI; capacitance; circuit analysis computing; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; coupling capacitance; coupling point admittance; crosstalk noise modeling; deep submicron VLSI chips; digital CMOS circuits; double pole approach; fast noise estimation method; interconnect branches; load modelling; lumped capacitor; multiple aggressor nets; optimization algorithms; physical design automation tools; reduction technique; resistive shielding effect modelling; signal integrity analysis; six-node template circuit; Capacitance; Capacitors; Circuit noise; Closed-form solution; Coupling circuits; Crosstalk; Design automation; Integrated circuit interconnections; Load modeling; Signal analysis;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.810741
Filename :
1196205
Link To Document :
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