Elementary limit cycles with application to the testing of digital circuits

Limit cycles in recursive digital filters are normally regarded as undesirable parasitic effects that one tries to minimize. However, one can also regard limit cycles as readily observable (and predictable) patterns of behavior that can be used to verify if a digital circuit is functioning properly. In this letter patterns of simple limit cycles that occur in first-order systems subject to some form of truncation or rounding, that are excited by a constant input, are investigated and classified in accordance with elementary number theory. The simplest of these result in input-output patterns that enable rapid verification of the correct functioning of simple combinations of adders and multipliers. As such they provide a useful method for testing this type of circuit in addition to conventional methods. Necessary and sufficient conditions for the following situations are derived: (i) a unique constant solution; (ii) a limit cycle of period 2 samples and of magnitude equal to m (integer), with m = 1 the most useful case; (iii) multiple constant solutions occurring in simple clusters; (iv) multiple limit cycles of type (ii) encircling a constant solution. Of these, type (ii) provides the most useful results for testing purposes. It is shown how the occurrence or nonoccurrence of limit cycles is related to increments in the value of u. It is also shown that limit cycles of period greater than 2 samples do not exist.