• DocumentCode
    1188584
  • Title

    A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

  • Author

    Hyde, John ; Humes, Todd ; Diorio, Chris ; Thomas, Mike ; Figueroa, Miguel

  • Author_Institution
    Impinj Inc., Seattle, WA, USA
  • Volume
    38
  • Issue
    5
  • fYear
    2003
  • fDate
    5/1/2003 12:00:00 AM
  • Firstpage
    734
  • Lastpage
    740
  • Abstract
    Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-μm CMOS logic processes. We trim the static integral nonlinearity to ±0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm2 of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.
  • Keywords
    CMOS integrated circuits; digital-analogue conversion; low-power electronics; system-on-chip; 0.18 micron; 0.25 micron; 14 bit; 250 MHz; 53 mW; analog charge; die area; digital-to-analog converter; floating-gate pFETs; floating-gate trimmed current-steered DAC; logic CMOS; on-chip electrical trimming; spur-free dynamic range; static integral nonlinearity; CMOS logic circuits; CMOS process; Digital-analog conversion; Dynamic range; Linearity; MOSFETs; Registers; Switches; Switching circuits; Tunneling;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2003.810049
  • Filename
    1196218
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1188584