Title :
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
Author :
Matano, Tatsuya ; Takai, Yasuhiro ; Takahashi, Tsugio ; Sakito, Yuusuke ; Fujii, Isamu ; Takaishi, Yoshihiro ; Fujisawa, Hiroki ; Kubouchi, Shuichi ; Narui, Seiji ; Arai, Koji ; Morino, Makoto ; Nakamura, Masayuki ; Miyatake, Shinichi ; Sekiguchi, Toshihi
Author_Institution :
Elpida Memory Inc., Kanagawa, Japan
fDate :
5/1/2003 12:00:00 AM
Abstract :
A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-μm 126.5-mm2 512-Mb chip.
Keywords :
CMOS memory circuits; DRAM chips; buffer circuits; current mirrors; delay lock loops; frequency dividers; 0.13 micron; 0.8 V; 1.6 V; 500 MHz; 512 Mbit; DDRII; SDRAM; current-mirror-type interpolator; digital DLL; duty-cycle correction; frequency divider; internal clocking; operating frequency; output skew; resolution; slew-rate impedance-controlled output buffer circuit; slew-rate-controlled output buffer; standby current; Circuit testing; Clocks; Delay; Frequency conversion; Impedance; Low voltage; SDRAM; Timing; Ultra large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.810030
