A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS

Author

Hegazi, Emad ; Abidi, Asad A.

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

Volume

38

Issue

5

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

782

Lastpage

792

Abstract

A fractional-N phase-locked loop (PLL) serves as a Gaussian minimum-shift keying (GMSK) transmitter and a receive frequency synthesizer for GSM. The entire transmitter/synthesizer is fully integrated in 0.35-μm CMOS and consumes 17.4 and 12 mW from 2.5 V in the transmit and receive modes, respectively, including an on-chip voltage-controlled oscillator. The circuit meets GSM specifications on modulation accuracy in transmit mode, and measured phase noise from the closed-loop PLL is -148 dBc/Hz and -162 dBc/Hz, respectively, at 3- and 20-MHz offset. Worst case spur at 13-MHz offset is -77 dBc.

Keywords

CMOS analogue integrated circuits; cellular radio; frequency synthesizers; minimum shift keying; phase locked loops; phase noise; radio transmitters; voltage-controlled oscillators; 0.35 micron; 12 mW; 17.4 mW; 2.5 V; 900 MHz; CMOS; GSM; Gaussian minimum-shift keying transmitter; closed-loop PLL; fractional-N phase-locked loop; frequency synthesizer; modulation accuracy; on-chip voltage-controlled oscillator; phase noise; transmit mode; worst case spur; Frequency synthesizers; GSM; Integrated circuit measurements; Noise measurement; Phase locked loops; Phase measurement; Phase modulation; Phase noise; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.810052

Filename

1196225