Title :
Memory requirements for the hardware implementation of decimators
fDate :
4/1/1983 12:00:00 AM
Abstract :
The tradeoffs between Memory requirements and Arithmetic Unit speed in the hardware implementation of decimators by FIR digital filters are discussed.
Keywords :
FIR (finite-duration impulse-response) digital filters; Signal sampling/reconstruction; Adders; Delay effects; Delay lines; Digital arithmetic; Digital filters; Finite impulse response filter; Frequency; Hardware; Sampling methods; Size control;
Journal_Title :
Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCS.1983.1085346
