Optimizing pipelined networks of associative and commutative operators

Author

Hartley, Richard ; Casavant, Albert E.

Author_Institution

Corp. Res. & Dev., Gen. Electr. Co., Schenectady, NY, USA

Volume

13

Issue

11

fYear

1994

fDate

11/1/1994 12:00:00 AM

Firstpage

1418

Lastpage

1425

Abstract

A method of tree-height minimization of networks of commutative and associative operators is described. The algorithm aims at minimizing latency and shimming delays in a synchronous data flow architecture such as that used in bit/digit-serial computation. The algorithm rearranges adder/subtractor trees to meet the joint goals, often allowing otherwise impossible scheduling constraints to be met. The algorithmic methods are found to apply also to trees of adders and shifters, such as those found in shift/add multipliers

Keywords

adders; digital arithmetic; iterative methods; logic CAD; pipeline processing; scheduling; trees (mathematics); adder/subtractor trees; associative operators; bit/digit-serial computation; commutative operators; pipelined networks; scheduling constraints; shift/add multipliers; shimming delays; synchronous data flow architecture; tree-height minimization; Adders; Circuits; Computer architecture; Delay; Iterative algorithms; Latches; Minimization methods; Optimal scheduling; Optimization methods; Scheduling algorithm;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.329271

Filename

329271