DocumentCode
1188997
Title
On determining symmetries in inputs of logic circuits
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Volume
13
Issue
11
fYear
1994
fDate
11/1/1994 12:00:00 AM
Firstpage
1428
Lastpage
1434
Abstract
We propose a method for computing maximal sets of symmetric inputs in logic circuits, using a test generation procedure for single stuck-at faults. The method is enhanced by a heuristic that can be used to identify nonsymmetric inputs and thus reduce the number of inputs for which test generation has to be carried out. We show the relevance of the problem to input matching for design diagnosis and for technology mapping. Experimental results demonstrate the effectiveness of the proposed procedures
Keywords
logic design; logic testing; set theory; design diagnosis; input matching; logic circuits; maximal sets; single stuck-at faults; symmetric inputs; technology mapping; test generation procedure; Circuit faults; Circuit testing; Cities and towns; Impedance matching; Libraries; Logic circuits; Logic design; Logic functions; Logic testing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.329273
Filename
329273
Link To Document