Multiple signature analysis method using fault simulation

This paper presents a signature analysis method that achieves a minimum aliasing rate. A fault stay map derived from exact fault simulation without fault dropping indicates whether a fault remains in an output data compressor at each time step. The fault stay map is used to determine the timing of multiple signature observations to achieve the minimum aliasing rate under certain constraints. Experimental results for some combinational circuits modeled on a single stuck-at fault are presented. They show that only two signature observations are required to achieve 0% aliasing in almost all circuits