Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

Author

Zhao, Peiyi ; McNeely, Jason B. ; Golconda, Pradeep K. ; Venigalla, Soujanya ; Wang, Nan ; Bayoumi, Magdy A. ; Kuang, Weidong ; Downey, Luke

Author_Institution

Math & Comput. Sci. Dept., Chapman Univ., Orange, CA, USA

Volume

17

Issue

9

fYear

2009

Firstpage

1196

Lastpage

1202

Abstract

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.

Keywords

CMOS logic circuits; MOSFET; flip-flops; low-power electronics; power supply circuits; CPN-LCFF; clustered voltage scaling; conditional discharge technique; dual supply system; level conversion; level-shifting scheme; low-power clocked-pseudo-NMOS flip-flop; n-type metal-oxide-semiconductor pass-transistor style; power dissipation; Dual supply; flip-flop; level conversion; low power;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2002426

Filename

4799223