Title :
Saving power by synthesizing gated clocks for sequential circuits
Author :
Benini, Luca ; Siegel, Polly ; De Micheli, Glovanni
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors´ technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.<>
Keywords :
clocks; finite state machines; logic design; sequential circuits; FSM; gated clocks; low power consumption; saving power; self-loops; sequential circuits; standard benchmarks; Automata; Circuit synthesis; Clocks; Costs; Energy consumption; Energy management; Laboratories; Latches; Sequential circuits; Signal synthesis;
Journal_Title :
Design & Test of Computers, IEEE
