Title :
SEE in a 0.15 μm fully depleted CMOS/SOI commercial Process
Author :
Makihara, A. ; Yamaguchi, T. ; Tsuchiya, Y. ; Arimitsu, T. ; Asai, H. ; Iide, Y. ; Shindou, H. ; Kuboyama, S. ; Matsuda, S.
Author_Institution :
High-Reliability Components Corp., Ibaraki, Japan
Abstract :
We evaluated single-event effects (SEEs) in test circuits fabricated at OKI with their 0.15 μm Fully Depleted CMOS/SOI commercial process. The sample devices were designed with hardness-by design (HBD) methodology. The results are discussed for an effective hardening design associated with SEEs.
Keywords :
CMOS integrated circuits; flip-flops; integrated circuit design; radiation hardening (electronics); silicon-on-insulator; 0.15 micron; Oki Electric Industry; SEE; circuits fabrication; effective hardening design; flip-flop; fully depleted CMOS-SOI commercial process; hardness-design methodology; latch; single-event effects; CMOS process; CMOS technology; Circuits; Degradation; Design methodology; Flip-flops; Isolation technology; Latches; Signal generators; Space technology;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2004.839155
