Title :
Edge triggered pulse latch design with delayed latching edge for radiation hardened application
Author :
Wang, Weizhong ; Gong, Haiyan
Author_Institution :
Electr. Eng. & Comput. Sci. Dept., Univ. of WisconsinMilwaukee, Milwaukee, WI, USA
Abstract :
We describe a novel edge triggered pulse latch design with delayed latching edge. Combined with dual interlocked cell (DICE) slave latch stage, the presented design is radiation hardened to both static single event upset (SEU) and dynamic single event transient (SET) on its internal sensitive nodes. Delayed latching edge design enables a new block level radiation hardening circuit design approach to trade timing resources in nontiming critical paths with the radiation hardness.
Keywords :
digital circuits; fault tolerance; flip-flops; logic circuits; radiation hardening (electronics); sequential circuits; shift registers; trigger circuits; SET; SEU; delayed latching edge; digital circuits; dual interlocked cell; dynamic single event transient; internal sensitive nodes; nontiming critical paths; novel edge triggered pulse latch design; radiation hardening; radiation hardening circuit design approach; registers; sequential logic circuit fault tolerance; slave latch stage; static single event upset; trade timing resources; Circuit synthesis; Clocks; Degradation; Delay; Flip-flops; Latches; Radiation hardening; Single event upset; Testing; Timing;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2004.839154
