Title :
Issues for single-event proton testing of SRAMs
Author :
Schwank, J.R. ; Dodd, P.E. ; Shaneyfelt, M.R. ; Felix, J.A. ; Hash, G.L. ; Ferlet-Cavrois, V. ; Paillet, P. ; Baggio, J. ; Tangyunyong, P. ; Blackmore, E.
Author_Institution :
Sandia Nat. Labs., Albuquerque, NM, USA
Abstract :
The impact of total ionizing dose and displacement damage on single-event upset and single-event latchup hardness assurance testing of present-day commercial SRAMs is studied over a wide range of proton energies and fluence levels. Commercial SRAMs from six different vendors were irradiated at proton energies from 8 to 500 MeV and at total doses from 0 to 100 krad(Si) using multiple radiation sources. For some SRAMs, the single-event upset cross section increased with total dose. The amount of increase in SEU cross section strongly depended on the bias configuration during total dose irradiation and single-event upset characterization. For most of the SRAMs that showed an increase in single-event upset cross section with total dose, the static power supply leakage current also increased. Light emission microscopy photographs identified the source of the increase in power supply leakage current for these SRAMs as originating in peripheral transistors outside the memory array. This suggests a new single-event upset mechanism for present-day devices, which may be due to a reduction in the internally supplied memory array bias level with total dose, increasing memory cell sensitivity to single-event upset. The proton energy at which the single-event latchup cross section saturated varied considerably between devices. For one technology, the single-event latchup cross section did not saturate until the proton energy was increased to 200 MeV. These data indicate that single-event latchup hardness assurance testing should be performed at high proton energies (>100 MeV). For fluence levels less than 1011 protons/cm2 at a proton energy of 105 MeV, proton-induced displacement damage had no observable affect on single-event latchup cross section. The implications of these effects on single-event upset and latchup hardness assurance testing are discussed.
Keywords :
SRAM chips; dosimetry; flip-flops; integrated circuit reliability; integrated circuit testing; leakage currents; proton effects; radiation hardening (electronics); 0 to 100 krad; SRAMs; bias configuration; displacement damage; fluence levels; integrated circuit reliability; integrated circuit testing; internally supplied memory array bias level; light emission microscopy photographs; memory cell sensitivity; multiple radiation sources; peripheral transistors; proton energy irradiation; proton testing; radiation effects; radiation hardening (electronics); radiation response; single event effects; single-event latchup cross section; single-event latchup hardness assurance testing; single-event proton testing; single-event upset cross section; static power supply leakage current; total ionizing dose irradiation; Circuit testing; Current supplies; Degradation; Leakage current; Power supplies; Protons; Random access memory; Single event upset; Space technology; Threshold voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2004.839301