DocumentCode :
1189689
Title :
Characterization of enhanced low dose rate sensitivity (ELDRS) effects using Gated Lateral PNP transistor structures
Author :
Pease, Ronald L. ; Platteter, Dale G. ; Dunham, G.W. ; Seiler, J.E. ; Barnaby, H.J. ; Schrimpf, R.D. ; Shaneyfelt, Marty R. ; Maher, M.C. ; Nowlin, R.N.
Author_Institution :
RLP Res., Los Lunas, NM, USA
Volume :
51
Issue :
6
fYear :
2004
Firstpage :
3773
Lastpage :
3780
Abstract :
The high and low dose rate responses of bipolar transistors in a bipolar linear circuit process technology have been studied with specially designed gated lateral pnp test transistors that allow for the extraction of the oxide trapped charge (Not) and interface trap (Nit) densities. The buildup of Not and Nit with total dose is investigated as a function of the irradiation gate voltage at 39 rad/s and 20 mrad/s for three variations of the final passivation layer (all variations had the same oxide covering the active region of the devices). The three variations in final passivation were selected to exhibit minimal degradation at high and low dose rate (no passivation), significant degradation at high and low dose rate (p-glass/nitride) and enhanced low dose rate sensitivity (ELDRS) (p-glass only). It is shown that the increase in base current is dominated by increased Nit and the "true" low dose rate enhancement in the ELDRS parts occurs for zero and negative gate voltage, but is eliminated for large positive gate voltage and elevated temperature irradiation. Implications for ELDRS models are discussed.
Keywords :
bipolar analogue integrated circuits; bipolar transistors; dosimetry; interface states; passivation; radiation effects; semiconductor device testing; base current; bipolar linear circuit process technology; bipolar transistors; device active region; elevated temperature irradiation; enhanced low dose rate sensitivity characterization effects; gated lateral pnp test transistor structures; high dose rate responses; interface trap densities; irradiation gate voltage; minimal degradation; oxide trapped charge; p-glass; p-glass/nitride; passivation layer; Bipolar transistor circuits; Bipolar transistors; Circuit testing; Cranes; Degradation; Linear circuits; Metastasis; Passivation; Temperature sensors; Voltage;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2004.839258
Filename :
1369557
Link To Document :
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