Title :
An Attempt to Design an Improved Multiplication System
Abstract :
Abstract—A speeded-up multiplication technique is considered wherein the two numbers to be multiplied are first examined and the one with the fewer 1´s is selected as the multiplier. It is found that the speeding-up diminishes towards 0 as the word length increases.
Keywords :
Index Terms—Algorithm, binary multiplication, series-parallel multiplication.; Circuits; Equations; Index Terms—Algorithm, binary multiplication, series-parallel multiplication.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1968.226864
