Abstract :
Abstract—The principal synthesis example of Schneider and Dietmeyer´s paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules.
Keywords :
Index Terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.; Algorithm design and analysis; Circuit synthesis; Combinational circuits; Costs; Delay; Design automation; Libraries; Logic design; Packaging; Upper bound; Index Terms—Circuit constraints, combinational logic synthesis, decomposition, design algorithm, design goals, logic design automation, module library.;
