A transport stream processor for HDD recording and playback of HDTV signal

Author

Sakurai, Masaru ; Nagata, Hidefumi ; Yamada, Masahiro ; Sakamoto, Noriya

Author_Institution

Dipital Media Network Co., Toshiba Corp., Tokyo, Japan

Volume

48

Issue

4

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

810

Lastpage

815

Abstract

This paper describes the architecture of the transport stream processor system for the digital HDTV receiver with HDD recording capability. The transport stream processor consists of a RISC processor, a content protection circuit, an IDE controller, and a bus interface. The transport stream processor generates the low clock rate partial transport streams by utilizing the bit rate control algorithm with the recording information table and the modulo algorithm. This system realizes a high-speed signal processing of multiple HDTV transport streams for HDD recording and playback for the storage digital broadcasting.

Keywords

controllers; digital television; high definition television; large scale integration; reduced instruction set computing; system buses; television receivers; video recording; video signal processing; HDD playback; HDD recording; HDTV signal; IDE controller; LSI; RISC processor; bit rate control algorithm; bus interface; content protection circuit; digital HDTV receiver; high-speed signal processing; low clock rate partial transport streams; modulo algorithm; recording information table; transport stream processor; transport stream processor system architecture; Bit rate; Circuits; Clocks; Digital recording; Digital signal processing; HDTV; Protection; Reduced instruction set computing; Signal processing; Signal processing algorithms;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2003.1196406

Filename

1196406