• DocumentCode
    118988
  • Title

    Adaptive sampling period adjusted sliding DFT for synchronous reference frame PLL

  • Author

    Chandrasekaran, S. ; Ragavan, K.

  • Author_Institution
    Dept. of Electr. Eng., Indian Inst. of Technol., Gandhinagar, Gandhinagar, India
  • fYear
    2014
  • fDate
    16-19 Dec. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Synchronous reference frame phase-locked loop (SRF PLL) is extensively employed for grid converter synchronization applications. When the input contains the fundamental positive sequence (FPS) component alone, it performs exceedingly well. However, with harmonic contamination and unbalance in the input, its performance degrades. For this purpose, many structural modifications are proposed. In this work, the sliding discrete Fourier transform (SDFT) is deployed as a pre-filter to the SRF PLL. However, under grid frequency drift, with fixed sampling frequency, the SDFT output becomes erroneous. To alleviate this problem, the sampling frequency is adaptively adjusted. Further, the unbalance in the input is dealt with the instantaneous symmetrical components method. Various grid fault scenarios are emulated with the help of dSPACE realtime controller board and the efficacy of the proposed scheme is demonstrated through experimental study.
  • Keywords
    discrete Fourier transforms; harmonics suppression; phase locked loops; power convertors; power grids; power system faults; power system harmonics; synchronisation; FPS; SDFT; SRF PLL; adaptive sampling period; dSPACE real-time controller board; fixed sampling frequency; fundamental positive sequence; grid converter synchronization application; grid fault scenario; harmonic contamination; prefilter sliding grid frequency drift; sliding DFT; sliding discrete Fourier transform; synchronous reference frame PLL; synchronous reference frame phase locked loop; Discrete Fourier transforms; Frequency synchronization; Harmonic analysis; Phase locked loops; Power system harmonics; Synchronization; Voltage fluctuations; Grid synchronization; phase estimation; phase-locked loop; sliding DFT;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Electronics, Drives and Energy Systems (PEDES), 2014 IEEE International Conference on
  • Conference_Location
    Mumbai
  • Print_ISBN
    978-1-4799-6372-0
  • Type

    conf

  • DOI
    10.1109/PEDES.2014.7041974
  • Filename
    7041974