Thermal model for paralleled surface-mount power MOSFETs

Power MOSFETs in surface-mount device (SMD) packages are used in circuit topologies with higher power density. Thermal modelling of these MOSFETs is necessary for estimating the allowable power loss. Use of explicit heatsink is not convenient in SMD MOSFETs compared to the through-hole packages. Hence, in many cases, it may be necessary to rely on natural air-cooling for the SMD MOSFETs. Paralleling of these MOSFETs is required in many applications for reducing the conduction losses and limiting temperature rise. In this paper, a prototype PCB and test setup are presented for obtaining the thermal model for paralleled SMD MOSFETs. It is also explained that the conventional correlations used for calculation of convective heat transfer coefficients do not apply to these devices, necessitating the need for experimental investigation. The thermal resistances obtained experimentally are significantly different compared to the datasheet values. A thermal resistance model is arrived at by using the results from experimental setup. It is shown that a thermal model based on a prototype circuit-board is an important step in optimizing the layout of the power converter.