Orthogonal digital filters for VLSI implementation

In this paper, an algorithm is developed for the realization of any stable, passive digital rational transfer function in a cascaded interconnection of similar processors with only nearest neighbor links. Extremely high throughput rates are shown to be achievable since the realization yields a pipelineable architecture. By appropriately choosing some normalization constants, limit cycle and overflow oscillations can also be eliminated. Experimental evidence is presented to show the low sensitivity of the structure with respect to perturbations of its parameters. The realization algorithm is extremely simple to implement, particularly for Butterworth, Chebyshev, and Elliptic Selective Filters. The procedure presented here is an outgrowth of certain results in stochastic estimation theory, involving in particular, the so-called fast Schur algorithm for lattice filters.