Title :
An FPGA implementation of a flexible architecture for H.263 video coding
Author :
Garrido, Matias J. ; Sanz, César ; Jiménez, Marcos ; Menesses, Juan M.
Author_Institution :
Univ. Politecnica de Madrid, Spain
fDate :
11/1/2002 12:00:00 AM
Abstract :
The architecture and design of MVIP-2, a flexible and efficient proposal for implementing an H.263 video coder, is explained in this paper. The MVIP-2 architecture consists of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The MVIP-2 design has been written in synthesizable hardware description language (HDL) and fully tested with hardware-software co-simulation using standard video sequences. Finally, MVIP-2 has been prototyped onto a system based on an FPGA and a RISC.
Keywords :
digital signal processing chips; field programmable gate arrays; hardware-software codesign; image sequences; processor scheduling; reduced instruction set computing; video codecs; FPGA; H.263 video coder; HDL; MVIP-2; RISC processor; flexible architecture; hardware-software co-simulation; motion compensation; motion estimation; quantizers; scheduling; specialized processors; standard video sequences; synthesizable hardware description language; transforms; Field programmable gate arrays; Hardware design languages; Motion compensation; Motion estimation; Processor scheduling; Proposals; Reduced instruction set computing; Testing; Video coding; Video sequences;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2003.1196439
