Upward topological analysis of large circuits using directed graph representation

This paper presents the method of topological analysis of large LLS networks with the use of hierarchical decomposition of the network graph. It is assumed that the network is represented by a directed graph. An algorithm of upward hierarchical analysis of a partitioned graph is presented. The algorithm allows symbolic analysis of large networks with the number of elements kept as symbols practically unlimited. The computational time linearly depends on the network size. A computer program using techniques described is also presented.