DocumentCode :
1191202
Title :
Optimisation efficiency in behavioural synthesis
Author :
Baker, K.R. ; Brown, A.D. ; Currie, A.J.
Author_Institution :
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
Volume :
141
Issue :
5
fYear :
1994
fDate :
10/1/1994 12:00:00 AM
Firstpage :
399
Lastpage :
406
Abstract :
Behavioural synthesis is the process whereby the mapping of system operation (behaviour) onto a physical circuit is essentially automated. In general, there are many ways in which a given design can be realised and each alternative design will have different physical parameters (area, speed and power dissipation being the most common). One of the key features of a good silicon compiler is that it allows the user to explore the `design space´ corresponding to the behavioural description; this means that the system must be capable of producing alternative (but behaviourally equivalent) designs relatively quickly. This paper describes the optimisation technique used in the MOODS (multiple objective optimisation behavioural synthesis) system and looks at the efficiency of the various subprocesses. The conclusions are that even for a large synthesis task, the time taken taken for MOODS to generate alternative designs is sufficiently low that the user response (in evaluating alternative designs) is essentially the rate limiting step in the overall design process. Typically, MOODS can generate 35 designs/second for a behavioural description containing 41 primitive operations running on a Sun SPARCstation LX
Keywords :
circuit layout CAD; optimisation; MOODS; Sun SPARCstation LX; automated mapping; behavioural synthesis; design space; multiple objective optimisation behavioural synthesis; optimisation efficiency; physical circuit; silicon compiler; system operation;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19941298
Filename :
329867
Link To Document :
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