Title :
Fast VLSI architectures using nonredundant multibit recoding for computing AY mod N
Author :
Prasanna, B.S. ; Mohan, P. V Ananda
Author_Institution :
Arcus Technol. Ltd., Bangalore, India
fDate :
10/1/1994 12:00:00 AM
Abstract :
A recently proposed technique for multiplication using two-bit recoding, which does not require subtraction operations, is extended for fast AB mod N evaluation. Architectures considering 2, 4, 8 and 16 bit recoding are considered and compared regarding the ALU complexity and speed requirements
Keywords :
VLSI; computational complexity; computer architecture; digital arithmetic; digital signal processing chips; ALU complexity; VLSI architecture; multiplication; nonredundant multibit recoding; speed requirements; two-bit recoding;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
DOI :
10.1049/ip-cds:19941166
