• DocumentCode
    1191764
  • Title

    Using simulated annealing in the minimisation of AND-EXOR functions

  • Author

    Parrilla, L. ; Ortega, Julio ; Lloris, A.

  • Author_Institution
    Dept. de Electron. y Tecnologia de Computadores, Granada Univ.
  • Volume
    30
  • Issue
    22
  • fYear
    1994
  • fDate
    10/27/1994 12:00:00 AM
  • Firstpage
    1838
  • Lastpage
    1839
  • Abstract
    Simulated annealing (SA) has been successfully used to solve problems in areas such as VLSI design, code design, image processing, etc., for which no tailored approximation algorithm is available. The authors propose the application of SA in the minimisation of switching functions that are expressed by using AND and EXOR gates. A procedure for AND-EXOR minimisation applying SA is described
  • Keywords
    logic gates; minimisation of switching nets; simulated annealing; switching functions; AND gates; AND-EXOR functions; EXOR gates; minimisation; simulated annealing; switching functions;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19941276
  • Filename
    329973
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1191764