Flag-oriented parallel associative architectures and applications

Author

Tavangarian, Djamshid

Author_Institution

Hagen Univ., Germany

Volume

27

Issue

11

fYear

1994

Firstpage

41

Lastpage

52

Abstract

Flag transformation, a new design concept for parallel associative memory and processor architectures, maps word-oriented data into flag-oriented data. A flag vector represents each word in a set. The flag position corresponds to the value of the transformed word, and all flags in a vector are processed simultaneously to obtain parallel operations. The results of complex search operations performed by modular, cascadable hardware components are also represented by flags and retransformed into word-oriented data. This transformation method allows parallel processing of associative or content-addressable data in uniprocessor architectures, expedites IC design rule checks, and accelerates complex memory tests. It can also be used to develop associative processor architectures and to emulate very fast, modular, cascadable artificial neural networks.<>

Keywords

associative processing; content-addressable storage; neural net architecture; parallel architectures; IC design rule checks; associative processor architectures; complex memory test acceleration; complex search operations; content-addressable data; flag transformation; flag vector; flag-oriented data; flag-oriented parallel associative architectures; modular, cascadable artificial neural networks; parallel associative memory; uniprocessor architectures; word-oriented data; Artificial neural networks; Associative memory; CADCAM; Computer aided manufacturing; Hardware; Memory architecture; Parallel processing; Programmable logic arrays; Random access memory; Registers;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.330031

Filename

330031