A bit-serial architecture for digital signal processing

This paper describes the architecture of a bit-serial VLSI circuit designed for digital signal processing applications. This circuit is capable of performing matrix-vector multiplications in a totally pipeline fashion. Although this circuit naturally performs multiplication of a matrix with a 3-element vector at a time, it can perform a (matrix) (vector) operation of any size. Under different control modes, the same architecture can also perform vector addition and scalar multiplication of vectors of arbitrary length. The circuit has been designed for a single chip implementation using 4 -NMOS technology. The word size of the chip is 16 bits, and the data is provided in 2\´s complement form. The chip contains approximately 6000 transistors in an area of 5.7 and operates with a 6-MHz two-phase clock in direct interface with a 6-MHz microprocessor. It can also be interfaced with a programmable digital signal processor. The chip is housed in a 64-pin DIP. A self-testing scheme incorporated into the design allows fault detection and isolation in a particular unit (storage or arithmetic unit) during the data processing.