DocumentCode
1192234
Title
Fast Memoryless,over 64 bits, residue-to-binary convertor
Author
Benardson, P.
Volume
32
Issue
3
fYear
1985
fDate
3/1/1985 12:00:00 AM
Firstpage
298
Lastpage
300
Abstract
This paper describes an algorithm and its hardware implementation which converts the 3 moduli
residue numbers into their binary representation. The given technique requires only binary adders, and no look-up tables. antages of this approach are two-fold: 1) It enables an extremely wide, fixed-point dynamic range, since its upper bound is not limited by a memory size. 2) The Integrated Circuit area required for its realization can be directly traded off with conversion speed. As a result, a 66-bit convertor with a conversion time of 120 ns, or a 36-bit one with 40 ns, may be implemented as single CMOS chips with 3
m geometries.
residue numbers into their binary representation. The given technique requires only binary adders, and no look-up tables. antages of this approach are two-fold: 1) It enables an extremely wide, fixed-point dynamic range, since its upper bound is not limited by a memory size. 2) The Integrated Circuit area required for its realization can be directly traded off with conversion speed. As a result, a 66-bit convertor with a conversion time of 120 ns, or a 36-bit one with 40 ns, may be implemented as single CMOS chips with 3
m geometries.Keywords
Memoryless systems; Residue arithmetic; Adders; Converters; Digital signal processing; Dynamic range; Equations; Geometry; Hardware; Signal processing algorithms; Table lookup; Upper bound;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1985.1085689
Filename
1085689
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