DocumentCode
1192775
Title
SILC and NBTI in pMOSFETs With Ultrathin SiON Gate Dielectrics
Author
Tsujikawa, Shimpei
Author_Institution
Renesas Technol. Corp., Hyogo
Volume
54
Issue
3
fYear
2007
fDate
3/1/2007 12:00:00 AM
Firstpage
524
Lastpage
530
Abstract
Degradation of pMOSFETs under negative gate bias stress has been intensively studied, bearing in mind the macroscopic and phenomenological similarity between stress-induced leakage current (SILC) and negative bias temperature instability (NBTI). By investigating the electrical characteristics of small-size pMOSFETs, the microscopic mechanisms of the degradation have been vividly revealed. In particular 1) NBTI-induced positive charge generation leading to a decrease in gate hole current and 2) some kind of leak path formation giving rise to SILC are found to occur in parallel, but not simultaneously. This finding enables us to conclude that SILC and NBTI in pMOS are not linked directly at least from the microscopic perspective despite their macroscopic similarity. These results have brought about new insights into the degradation of pMOS under negative gate bias, which is now quite important to CMOS reliability
Keywords
CMOS integrated circuits; MOSFET; electric breakdown; interface states; leakage currents; NBTI; SILC; TDDB; bulk trap; interface trap; negative bias temperature instability; pMOS; pMOSFET; stress induced leakage current; thin gate dielectric; time dependent dielectric breakdown; ultrathin SiON gate dielectrics; Degradation; Dielectrics; Electric variables; Leakage current; MOSFETs; Microscopy; Negative bias temperature instability; Niobium compounds; Stress; Titanium compounds; Bulk trap; interface trap; negative bias temperature instability (NBTI); pMOS; recovery; stress-induced leakage current (SILC); thin gate dielectric; time-dependent dielectric breakdown (TDDB);
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2006.890382
Filename
4114864
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