• DocumentCode
    1192891
  • Title

    Design of a simple two´s complement multiplier circuit

  • Author

    Ahmad, M.O. ; Sundararajan, D.

  • Volume
    32
  • Issue
    6
  • fYear
    1985
  • fDate
    6/1/1985 12:00:00 AM
  • Firstpage
    622
  • Lastpage
    624
  • Abstract
    A design and hardware implementation of a simple 2´s complement multiplier is presented. The speed of the operation is evaluated and compared with experimental results.
  • Keywords
    Multiplication; Circuit testing; Circuits and systems; Clocks; Flip-flops; Flowcharts; Hardware; Pulse circuits; Signal processing; Space vector pulse width modulation; System recovery;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-4094
  • Type

    jour

  • DOI
    10.1109/TCS.1985.1085752
  • Filename
    1085752
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1192891