Title :
X-Align: Improving the Scan Cell Observability of Response Compactors
Author :
Sinanoglu, Ozgur ; Almukhaizim, Sobeeh
Author_Institution :
Dept. of Math. & Comput. Sci., Kuwait Univ., Safat, Kuwait
Abstract :
While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Unknown x´s further exacerbate the quality loss problem, as they mask out errors captured in other scan cells in the presence of response compactors. In this paper, we propose a technique that manipulates the x distribution in scan responses prior to their propagation into the response compactor. A block, which we refer to as x-align, inserted between the scan chains and the response compactor aligns response x´s within the same slices as much as possible in order to increase the number of scan cells that can be observed through the compactor. The alignment of x´s is achieved by delaying the scan-out operations in the scan chains, wherein the proper delay values are computed judiciously. We present an Integer Linear Programming (ILP) formulation and a computationally efficient greedy heuristic for the computation of the delay values for scan chains. The x-align hardware is generic yet reconfigurable. An analysis of x distribution in a captured response helps compute the proper delay values, with which x-align is reconfigured to maximize the alignment of x´s. The scan cell observability enhancement delivered by x-align paves the way for the utilization of simple response compactors, such as parity trees, yet providing high levels of test quality even in the presence of a large density of response x´s. X-align can also be utilized with any response compactor to manipulate the x distribution in favor of the compactor, thus improving the test quality attained.
Keywords :
circuit testing; integer programming; linear programming; error masking; greedy heuristic; integer linear programming; parity trees; quality loss problem; response compactors; scan cell observability; scan chains; scan-out operations; tester memory; x-align hardware; Error masking; output compaction; test response compaction; unknown response bits; x-align;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2004589