DocumentCode
1193549
Title
Accumulation of product roundoff errors in modified FFT´s
Author
Chowdary, Nuthalapati ; Steenaart, Willem
Volume
33
Issue
1
fYear
1986
fDate
1/1/1986 12:00:00 AM
Firstpage
103
Lastpage
107
Abstract
In this paper, expressions are derived for the mean square error in modified radix-2 FFT algorithms. To reduce the mean square error at the output of a special purpose, high-speed low-order 
FFT processor implemented in fixed-point arithmetic, a modified FFT architecture is considered in which an extra bit is added to the register wordlength to prevent overflow. In this way, the scaling error is avoided and only the error due to product roundoff remains, in the case of implementation with stored-product ROM multipliers. The predicted signal/noise ratios are compared with those obtained by computer simulation.
FFT processor implemented in fixed-point arithmetic, a modified FFT architecture is considered in which an extra bit is added to the register wordlength to prevent overflow. In this way, the scaling error is avoided and only the error due to product roundoff remains, in the case of implementation with stored-product ROM multipliers. The predicted signal/noise ratios are compared with those obtained by computer simulation.Keywords
DFT; Discrete Fourier transforms (DFT´s); Finite-wordlength effects; Computer errors; Computer simulation; Fixed-point arithmetic; Hardware; Mean square error methods; Quantization; Read only memory; Registers; Roundoff errors; Signal to noise ratio;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/TCS.1986.1085820
Filename
1085820
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