• DocumentCode
    1193694
  • Title

    Improved domino logic for high speed design

  • Author

    Jia, Song ; Liu, Fei ; Ji, Lijiu

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • Volume
    39
  • Issue
    8
  • fYear
    2003
  • fDate
    4/17/2003 12:00:00 AM
  • Firstpage
    644
  • Lastpage
    645
  • Abstract
    Techniques are introduced to improve the speed of domino logic. With an inverted clock scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. HSPICE simulation shows that over 20% performance enhancement is achieved.
  • Keywords
    CMOS logic circuits; capacitance; high-speed integrated circuits; integrated circuit design; logic design; timing; CMOS logic style; domino logic; high performance design; high speed design; inverted clock scheme; output node capacitance reduction;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20030422
  • Filename
    1197976
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1193694