DocumentCode :
1193709
Title :
Interests and Limitations of Technology Scaling for Subthreshold Logic
Author :
Bol, David ; Ambroise, Renaud ; Flandre, Denis ; Legat, Jean-Didier
Author_Institution :
Microelectron. Lab., Univ. catholique de Louvain, Louvain, Belgium
Volume :
17
Issue :
10
fYear :
2009
Firstpage :
1508
Lastpage :
1519
Abstract :
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded subthreshold swing and delay variability. Moreover, for low-throughput applications (10-100 kHz), this limitation is worsened by the increase of minimum supply voltage to achieve sufficient functional yield, which results in bad energy efficiency starting at 0.13 mum node. Upsizing the channel length is proposed as a straightforward circuit-level technique to efficiently mitigate these effects. At 32 nm node, this technique reduces energy per operation by 60% at medium throughput and by two orders of magnitude at low throughput.
Keywords :
energy conservation; scaling circuits; threshold logic; channel length up-sizing; delay variability; dynamic energy reduction; energy efficiency; functional yield; static energy; subthreshold logic; subthreshold swing; technology scaling; ultralow power consumption; CMOS digital integrated circuits; subthreshold logic; technology scaling; ultralow power (ULP); variability;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2008.2005413
Filename :
4801587
Link To Document :
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