Title :
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction
Author :
Zhe Wang ; Murgai, R. ; Roychowdhury, J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
Estimating interference from large digital blocks, and its effect on on-chip power-distribution networks, is extremely important in deep submicron digital and mixed-signal IC design, especially for systems-on-a-chip. In this paper, we present automated extraction techniques that can be used to generate families of small, time-varying macromodels of digital cell libraries from SPICE-level descriptions. Our automated digital aggressor macromodeling for interference noise (ADAMIN) approach is based on importing and adapting the time-varying Pade/spl acute/ method, for linear time-varying model reduction, from the mixed-signal macromodeling domain. Our approach features naturally higher accuracy than previous ones and, in addition, offers the user a tradeoff between accuracy and macromodel complexity. Extracted macromodels capture a variety of noise interference mechanisms, including IR and L(dI/dT) drops for power rails. Using ADAMIN as a core, it is expected that library-characterization methodologies will evolve to include extracted, accurate-by-construction interference noise macromodels for digital cell blocks. Experimental results indicate speedups of several orders of magnitude over full SPICE-level circuits, with prediction accuracies considerably superior to those from commonly-used current-source-based aggressor models.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; mixed analogue-digital integrated circuits; reduced order systems; system-on-chip; ADAMIN; Pade method; SPICE-level descriptions; automated digital aggressor macromodeling for interference noise; automated extraction techniques; deep submicron digital IC design; digital cell libraries; digital switching; ground supply noise prediction; interference estimation; linear time-varying model reduction; mixed-signal IC design; noise interference mechanisms; on-chip power-distribution networks; power rails; power supply noise prediction; systems-on-a-chip; Circuit noise; Digital integrated circuits; Integrated circuit noise; Interference; Network-on-a-chip; Noise reduction; Power supplies; Reduced order systems; Software libraries; System-on-a-chip; Aggressor; digital switching; glitch; interference; substrate noise; supply noise; victim;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2004.839470