A systolic SBNR adaptive signal processor

A new realization for adaptive signal processing units is proposed which uses a special subset of signed digit number representations (SDNR´s). This signed binary number representation (SBNR) captures all of the efficiencies of SDNR arithmetic but also makes circuit realizations less complex. Furthermore, a natural interface between analog and digital numbers is provided. The serial on-line processing nature of SBNR utilizes the MSB first. An area/time complexity for VLSI implementations in comparable systolic array architectures contrasts the effectiveness of five different primitive VLSI cells and organizations.