• DocumentCode
    1194309
  • Title

    Passive multiplexer test structure for fast and accurate contact and via fail-rate evaluation

  • Author

    Hess, Christopher ; Stine, Brian E. ; Weiland, Larg H. ; Mitchell, Todd ; Karnett, Martin P. ; Gardner, Keith

  • Author_Institution
    PDF Solutions Inc., San Jose, CA, USA
  • Volume
    16
  • Issue
    2
  • fYear
    2003
  • fDate
    5/1/2003 12:00:00 AM
  • Firstpage
    259
  • Lastpage
    265
  • Abstract
    The complexity of integrated circuits has led to millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of <10 faults per billion, which requires test structures with huge chains of 1 million or more contacts and vias. At the same time, contacts and vias are getting smaller, and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a passive multiplexer array of via chains, which breaks up a huge contact-via chain into many individually measurable subchains. Accuracy of fail rates is increased since the fail rate can be determined based on many subchains rather than on only one huge chain. Furthermore, this test structure better supports failure analysis since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging.
  • Keywords
    CMOS integrated circuits; electric resistance measurement; failure analysis; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; multiplexing; CMOS process; contact fail-rate evaluation; contact-via chain resistance measurement; fail rate accuracy; failure analysis; fast process problem debugging; passive multiplexer test structure; via fail-rate evaluation; yield evaluation; Circuit faults; Circuit testing; Contact resistance; Debugging; Electrical resistance measurement; Failure analysis; Helium; Integrated circuit interconnections; Integrated circuit yield; Multiplexing;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2003.811939
  • Filename
    1198038