Timing analysis for piecewise linear Rsim

Rsim is a switch-level simulator that can simulate large digital MOS integrated circuits up to three orders of magnitude faster than SPICE. Unfortunately, Rsim´s simplified circuit models and timing analysis prevent it from simulating “difficult” CMOS circuits and circuits containing bipolar transistors. We address this shortcoming by adapting Rsim to use more general piecewise linear models. We show that these modifications can be made in a way that preserves Rsim´s efficiency for the simplest cases. The result is a simulator that can approach the efficiency of dedicated switch-level simulators when switch-level models are used. Alternatively, greater accuracy and flexibility can be obtained when more sophisticated models are used