RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes

This paper presents RESIST, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scanbased circuits. Five test classes are introduced and their properties are discussed. We present an algorithm for deriving a logic system for TPG that results in an earlier recognition of conflicting value assignments. RESIST uses the logic system derived for each test class for an optimal search strategy. In contrast to other approaches, it exploits the fact that many paths in a circuit have common subpaths. RESIST sensitizes those subpaths only once, reducing the number of value assignments during path sensitization significantly. In addition, our procedure identifies large sets of untestable path delay faults without enumerating them. RESIST is capable of performing TPG for all path delay faults in all ISCAS-85 and ISCAS-89 circuits. For the first time, results for all path delay faults in circuit c6288 are presented. A comparison with other TPG systems revealed that RESIST is significantly faster than all previously published methods