Abstract :
Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of VDB =55 V (Rsp=0.2 mΩ-cm2, k D=5.7 Ω-pF) and VDB=35 V (Rsp=0.15 mΩ-cm2, kD =4.3 Ω-PF) were developed where VDB is the drain-source avalanche breakdown voltage, Rsp is the specific on-state resistance, and kD=R spCsp is the input device technology factor where Csp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model
Keywords :
insulated gate field effect transistors; oxidation; power transistors; semiconductor technology; sputter etching; 35 V; 55 V; RIE process; analytical model; drain-source avalanche breakdown voltage; forward conductivities; input device technology factor; polysilicon gate planarization technique; power MOSFETs; sequential oxidation/oxide etchback; specific MOS gate input capacitance; specific on-state resistance; surface damage; trench MOSFET technologies; trench processing technology; trench sidewall cleaning; two-dimensional device simulations; vertical trench power MOSFET; Analytical models; Avalanche breakdown; Breakdown voltage; Capacitance measurement; Conductivity; MOSFET circuits; Performance evaluation; Power MOSFET; Power measurement; Silicon;
