Switched-capacitor algorithmic digital-to-analog converters

Novel switched-capacitor circuits for algorithmic digital-to-analog conversion are described. The conversion process is insensitive both to the offset voltages of op-amps and to parasitic capacitances. The capacitance mismatch errors are also minimized because only a small number of unit capacitors are used. An error analysis is presented that shows an accuracy greater than 10-bits can be obtained using present MOS technologies. Besides being very accurate, the new converters possess the important feature of being integrable using only a minimal amount of chip area.