Gain-enhanced LDD NMOS device using cesium implantation

Author

Pfiester, James R. ; Alvis, John R. ; Gunderson, Craig D.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

39

Issue

6

fYear

1992

fDate

6/1/1992 12:00:00 AM

Firstpage

1469

Lastpage

1476

Abstract

A gain-enhanced LDD NMOS device has been developed for a submicrometer CMOS technology. Using cesium implantation to create a fixed positive charge at the oxide/silicon interface above the LDD region, improvements in device gain are obtained without degradation to hot-carrier reliability or short-channel behavior. Since fixed charge rather than an extended polysilicon gate is used to overlap the LDD regions, no penalty is paid in terms of extra gate overlap capacitance. Furthermore, this structure is easily integrated into a conventional twin-tub CMOS process with the addition of only one cesium implantation step which is performed at the same time as the LDD n^- implant step

Keywords

CMOS integrated circuits; caesium; hot carriers; insulated gate field effect transistors; integrated circuit technology; ion implantation; MOSFET; Si:Cs⁺-SiO₂; device gain; fixed positive charge; gain-enhanced LDD NMOS device; gate overlap capacitance; hot-carrier reliability; ion implantation; short-channel behavior; submicrometer CMOS technology; twin-tub CMOS process; CMOS process; CMOS technology; Capacitance; Degradation; Electrons; Hot carriers; Implants; MOS devices; MOSFETs; Silicon;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.137328

Filename

137328