Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip

In practice, a chip multiprocessor (CMP) with many nodes often runs multiple applications simultaneously and nodes allocated to different applications seldom communicate. Leveraging the non-uniformity of communication, it is possible to optimize the Network-on-Chip (NoC) performance for the case of single chip running multiple applications through reducing the physical links lengths between nodes which tend to be allocated to the same application. In this paper, we propose a novel, nearly zero-cost floor plan method called Archipelago which rearranges the lengths of physical links by flipping hard IP of nodes. With communication monitoring and dynamic thread scheduling, Archipelago significantly reduces the average latency of NoC for concurrent multiple small- and medium-size applications. Experimental results show that Archipelago averagely reduces the packet latency by 19.10% and maximum to 24.4% for three-node applications on 4 × 4 mesh NoC.