A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout

Author

Ng, K.A. ; Chan, P.K.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

Volume

52

Issue

10

fYear

2005

Firstpage

2065

Lastpage

2074

Abstract

A new time-multiplexed switched-capacitor (TM-SC) equalizer is designed on the basis of the previously reported correlated double-sampling integrator and the crosstalk reduction layout approach, which aims at improving the performance aspects on crosstalk, gain loss, 1/f noise and offset. The equalizer, which operates at a single 3-V supply and has a filter bank with 4TM channels, has been fabricated to confirm the effectiveness of the structure using a standard 0.8-μm CMOS process.

Keywords

CMOS integrated circuits; channel bank filters; crosstalk; equalisers; integrated circuit layout; integrating circuits; switched capacitor filters; 0.8 micron; 3 V; CDS equalizer; CMOS process; correlated double sampling equalizer; correlated double-sampling integrator; crosstalk layout; crosstalk reduction layout approach; filter bank; integrated circuit; switched-capacitor circuit; time-multiplexed circuit; time-multiplexed switched-capacitor equalizer; Circuit synthesis; Crosstalk; Equalizers; Filters; Noise reduction; Performance gain; Semiconductor device noise; Silicon; Switching circuits; Working environment noise; Crosstalk; equalizers; integrated circuit; layout; switched-capacitor (SC) circuit; time-multiplexed (TM) circuit;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2005.852921

Filename

1519620